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using_arm_caches [2014/05/31 21:35]
bain [Special L2C-310 + Cortex-A9 MPCore Options]
using_arm_caches [2014/06/11 12:40] (current)
bain
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   * ARM Cortex-A9 Technical Reference Manual [[http://​infocenter.arm.com/​help/​topic/​com.arm.doc.ddi0388i/​index.html|Cortex-A9 TRM]]   * ARM Cortex-A9 Technical Reference Manual [[http://​infocenter.arm.com/​help/​topic/​com.arm.doc.ddi0388i/​index.html|Cortex-A9 TRM]]
   * ARM Cortex-A9 MPCore Technical Reference Manual [[http://​infocenter.arm.com/​help/​topic/​com.arm.doc.ddi0407i/​index.html|Cortex-A9 MPCore TRM]]   * ARM Cortex-A9 MPCore Technical Reference Manual [[http://​infocenter.arm.com/​help/​topic/​com.arm.doc.ddi0407i/​index.html|Cortex-A9 MPCore TRM]]
-  * Level 2 Cache Controller (L2C-310) Technical Reference Manual [[http://​infocenter.arm.com/​help/​index.jsp?topic=/​com.arm.doc.ddi0246e/​index.html|L2C-310 TRM]]+  * Level 2 Cache Controller (L2C-310) Technical Reference Manual [[http://​infocenter.arm.com/​help/​topic/​com.arm.doc.ddi0246h/​index.html|L2C-310 TRM]]
  
 The ARM processor in the Cyclone V has both L1 and L2 caches. The ARM processor in the Cyclone V has both L1 and L2 caches.
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 Several other options area available as well. Several other options area available as well.
 Both the Cortex-A9 TRM and L2C-310 TRM (linked above) outline several optimizations for L2 memory accesses. Both the Cortex-A9 TRM and L2C-310 TRM (linked above) outline several optimizations for L2 memory accesses.
-[[http://​infocenter.arm.com/​help/​topic/​com.arm.doc.ddi0246e/​CJACBHHB.html|Link]].+[[http://​infocenter.arm.com/​help/​topic/​com.arm.doc.ddi0246h/​CJACBHHB.html|Link]].
  
 The following features are available when using the L2C-310 cache controller with a Cortex-A9 MPCore processor: The following features are available when using the L2C-310 cache controller with a Cortex-A9 MPCore processor:
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 +====== Source Code ======
 +This investigation resulted in two files: arm_cache.h and arm_cache.s that together provide functions to turn on the MMU and caches on the ARM Cortex-A9 MPCore in the Altera Cyclone V SoC.
 +
 +   * [[https://​www.dropbox.com/​s/​l2mzqzfq3089emj/​arm_cache.h | arm_cache.h]]
 +   * [[https://​www.dropbox.com/​s/​tq6y2yod3p26yui/​arm_cache.s | arm_cache.s]]
  
  
using_arm_caches.1401586523.txt.gz ยท Last modified: 2014/05/31 21:35 by bain