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using_arm_caches

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Using ARM Caches

This page describes how to set up caching on the Cortex-A9 MPCore processor found in the Cyclone V.

Introduction

The following documents are useful references:

The processor in the Cyclone V has both L1 and L2 caches. The L1 cache is split into separate instruction and data caches and is controlled directly by the processor. The L2 cache is a unified cache and is controlled by the L2C-310 cache controller.

The L1 instruction cache can be enabled using a single bit in the SCTLR register using MRC/MCR instructions. The L1 data cache can only be used when the memory management unit (MMU) is on. The L2 cache can be enabled by programming the L2C-310 controller using memory-mapped registers.

To see how the processor performs in various configurations, see the benchmarking results at ARM Benchmark Results.

Enabling the MMU

The MMU serves to translate virtual addresses used by the processor into physical addresses that correspond to actual memory locations. It also controls the caching behaviour of different sections of the memory space.

Several steps are involved when turning on the MMU:

  • Disable caches and branch predictor
  • Invalidate instruction, data, and unified TLBs, L1 instruction and data caches, and branch predictor array
  • Set up translation table entries
  • Set translation table control registers
  • Set domain access control register
  • Enable the MMU

Programming the L2 Cache Controller

The L2C-310 cache controller is controlled using memory mapped registers. For the Cyclone V SoC the base address for these registers is 0xFFFEF000.

The following steps are to be taken to enable the L2 cache controller:

  • Set the Way size
  • Set the read, write, and hold delays for Tag RAM
  • Set the read, write, and hold delays for Data RAM
  • Set the prefetching behaviour
  • Invalidate the cache
  • Enable the L2C-310 cache controller

Memory Optimizations

The following settings can greatly enhance memory performance:

  • Enable L1 Data-side prefetch
  • Set memory region attributes in TTB entries
  • Use minimum stable L2C-310 read, write, and hold delays

The following features are available when using the L2C-310 cache controller with a Cortex-A9 MPCore processor:

  • Exclusive caching
  • L2 prefetch hints
  • Early BRESP
  • Writing a full line of zeros
  • L2 cache speculative linefill

These features were all tested during benchmarking, however

using_arm_caches.1401581046.txt.gz · Last modified: 2014/05/31 20:04 by bain