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Using ARM Caches

This page describes how to set up caching on the Cortex-A9 MPCore processor found in the Cyclone V.


The following documents are useful references:

The processor in the Cyclone V has both L1 and L2 caches. The L1 cache is split into separate instruction and data caches and is controlled directly by the processor. The L2 cache is a unified cache and is controlled by the L2C-310 cache controller.

The L1 instruction cache can be enabled using a single bit in the SCTLR register using MRC/MCR instructions. The L1 data cache can only be used when the memory management unit (MMU) is on. The L2 cache can be enabled by programming the L2C-310 controller using memory-mapped registers.

Enabling the MMU

The MMU serves to translate virtual addresses used by the processor into physical addresses that correspond to actual memory locations. It also controls the caching behaviour of different sections of the memory space.

Several steps are involved when turning on the MMU:

  • Disable caches and branch predictor
  • Invalidate instruction, data, and unified TLBs, L1 instruction and data caches, and branch predictor array
  • Set up translation table entries
  • Set translation table control registers
  • Set domain access control register
  • Enable the MMU

Programming the L2 Cache Controller

Memory Optimizations

using_arm_caches.1401580177.txt.gz · Last modified: 2014/05/31 19:49 by bain