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undergrad_intern_projects [2016/09/21 15:46] (current)
janders created
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 +2016 Ideas
  
 +  * Enhance timing modelling to account for bitwidth minimization.
 +  * Shrink array memory width based on bidwidth minimization (loads already account for reduced width).
 +  * Xilinx performance improvement
 +  * If-conversion "​productization"​ and experimentation
 +  * 
undergrad_intern_projects.txt ยท Last modified: 2016/09/21 15:46 by janders