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#include "hps_0.h"

#define HW_REGS_BASE ( ALT_STM_OFST )
#define HW_REGS_SPAN ( 0x04000000 )
#define HW_REGS_MASK ( HW_REGS_SPAN - 1 )

int main() {
// map the address space for the LED registers into user space so we can
// interact with them.
// we'll actually map in the entire CSR span of the HPS since we want to access
//various registers within that span

	if( ( fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) ) ) == -1 ) {
		printf( "ERROR: could not open \"/dev/mem\"...\n" );
		return( 1 );
	}

	virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ),
					MAP_SHARED, fd, HW_REGS_BASE );

	if( virtual_base == MAP_FAILED ) {
		printf( "ERROR: mmap() failed...\n" );
		close( fd );
		return( 1 );
	}
	
	h2p_lw_led_addr=virtual_base + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST +
				PIO_LED_BASE ) & ( unsigned long)( HW_REGS_MASK ) );
	
	//read/write to it
	Int led_mask = 0x2ff;
	//Flash LEDs 10 times
	for (int i=0; i<10; i++) {
		*(uint32_t *)h2p_lw_led_addr =  led_mask; //turn on all LEDs
		usleep(500*1000); //wait 500ms
		*(uint32_t *)h2p_lw_led_addr =  ~led_mask; //turn of all LEDs
	}
	
	
	//clean it up
	if( munmap( virtual_base, HW_REGS_SPAN ) != 0 ) {
		printf( "ERROR: munmap() failed...\n" );
		close( fd );
		return( 1 );
	}

	close( fd );
	
}

#ifndef _ALTERA_HPS_0_H_
#define _ALTERA_HPS_0_H_

/*
 * This file was automatically generated by the swinfo2header utility.
 * 
 * Created from SOPC Builder system 'soc_system' in
 * file './soc_system.sopcinfo'.
 */

/*
 * This file contains macros for module 'hps_0' and devices
 * connected to the following masters:
 *   h2f_axi_master
 *   h2f_lw_axi_master
 * 
 * Do not include this header file and another header file created for a
 * different module or master group at the same time.
 * Doing so may result in duplicate macro names.
 * Instead, use the system header file which has macros with unique names.
 */

/*
 * Macros for device 'gpu_status_out_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'GPU_STATUS_OUT_PIO_'.
 * The prefix is the slave descriptor.
 */
#define GPU_STATUS_OUT_PIO_COMPONENT_TYPE altera_avalon_pio
#define GPU_STATUS_OUT_PIO_COMPONENT_NAME gpu_status_out_pio
#define GPU_STATUS_OUT_PIO_BASE 0x0
#define GPU_STATUS_OUT_PIO_SPAN 64
#define GPU_STATUS_OUT_PIO_END 0x3f
#define GPU_STATUS_OUT_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define GPU_STATUS_OUT_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPU_STATUS_OUT_PIO_CAPTURE 0
#define GPU_STATUS_OUT_PIO_DATA_WIDTH 32
#define GPU_STATUS_OUT_PIO_DO_TEST_BENCH_WIRING 0
#define GPU_STATUS_OUT_PIO_DRIVEN_SIM_VALUE 0
#define GPU_STATUS_OUT_PIO_EDGE_TYPE NONE
#define GPU_STATUS_OUT_PIO_FREQ 50000000
#define GPU_STATUS_OUT_PIO_HAS_IN 0
#define GPU_STATUS_OUT_PIO_HAS_OUT 1
#define GPU_STATUS_OUT_PIO_HAS_TRI 0
#define GPU_STATUS_OUT_PIO_IRQ_TYPE NONE
#define GPU_STATUS_OUT_PIO_RESET_VALUE 0

/*
 * Macros for device 'gpu_status_in_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'GPU_STATUS_IN_PIO_'.
 * The prefix is the slave descriptor.
 */
#define GPU_STATUS_IN_PIO_COMPONENT_TYPE altera_avalon_pio
#define GPU_STATUS_IN_PIO_COMPONENT_NAME gpu_status_in_pio
#define GPU_STATUS_IN_PIO_BASE 0x10
#define GPU_STATUS_IN_PIO_SPAN 64
#define GPU_STATUS_IN_PIO_END 0x4f
#define GPU_STATUS_IN_PIO_IRQ 4
#define GPU_STATUS_IN_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define GPU_STATUS_IN_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPU_STATUS_IN_PIO_CAPTURE 1
#define GPU_STATUS_IN_PIO_DATA_WIDTH 32
#define GPU_STATUS_IN_PIO_DO_TEST_BENCH_WIRING 0
#define GPU_STATUS_IN_PIO_DRIVEN_SIM_VALUE 0
#define GPU_STATUS_IN_PIO_EDGE_TYPE ANY
#define GPU_STATUS_IN_PIO_FREQ 50000000
#define GPU_STATUS_IN_PIO_HAS_IN 1
#define GPU_STATUS_IN_PIO_HAS_OUT 0
#define GPU_STATUS_IN_PIO_HAS_TRI 0
#define GPU_STATUS_IN_PIO_IRQ_TYPE EDGE
#define GPU_STATUS_IN_PIO_RESET_VALUE 0

/*
 * Macros for device 'gpu_out_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'GPU_OUT_PIO_'.
 * The prefix is the slave descriptor.
 */
#define GPU_OUT_PIO_COMPONENT_TYPE altera_avalon_pio
#define GPU_OUT_PIO_COMPONENT_NAME gpu_out_pio
#define GPU_OUT_PIO_BASE 0x20
#define GPU_OUT_PIO_SPAN 64
#define GPU_OUT_PIO_END 0x5f
#define GPU_OUT_PIO_IRQ 3
#define GPU_OUT_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define GPU_OUT_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPU_OUT_PIO_CAPTURE 1
#define GPU_OUT_PIO_DATA_WIDTH 32
#define GPU_OUT_PIO_DO_TEST_BENCH_WIRING 0
#define GPU_OUT_PIO_DRIVEN_SIM_VALUE 0
#define GPU_OUT_PIO_EDGE_TYPE ANY
#define GPU_OUT_PIO_FREQ 50000000
#define GPU_OUT_PIO_HAS_IN 1
#define GPU_OUT_PIO_HAS_OUT 0
#define GPU_OUT_PIO_HAS_TRI 0
#define GPU_OUT_PIO_IRQ_TYPE EDGE
#define GPU_OUT_PIO_RESET_VALUE 0

/*
 * Macros for device 'alt_vip_vfr_vga', class 'alt_vip_vfr'
 * The macros are prefixed with 'ALT_VIP_VFR_VGA_'.
 * The prefix is the slave descriptor.
 */
#define ALT_VIP_VFR_VGA_COMPONENT_TYPE alt_vip_vfr
#define ALT_VIP_VFR_VGA_COMPONENT_NAME alt_vip_vfr_vga
#define ALT_VIP_VFR_VGA_BASE 0x100
#define ALT_VIP_VFR_VGA_SPAN 512
#define ALT_VIP_VFR_VGA_END 0x2ff

/*
 * Macros for device 'sysid_qsys', class 'altera_avalon_sysid_qsys'
 * The macros are prefixed with 'SYSID_QSYS_'.
 * The prefix is the slave descriptor.
 */
#define SYSID_QSYS_COMPONENT_TYPE altera_avalon_sysid_qsys
#define SYSID_QSYS_COMPONENT_NAME sysid_qsys
#define SYSID_QSYS_BASE 0x10000
#define SYSID_QSYS_SPAN 8
#define SYSID_QSYS_END 0x10007
#define SYSID_QSYS_ID 2899645186
#define SYSID_QSYS_TIMESTAMP 1427848650

/*
 * Macros for device 'led_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'LED_PIO_'.
 * The prefix is the slave descriptor.
 */
#define LED_PIO_COMPONENT_TYPE altera_avalon_pio
#define LED_PIO_COMPONENT_NAME led_pio
#define LED_PIO_BASE 0x10040
#define LED_PIO_SPAN 64
#define LED_PIO_END 0x1007f
#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_DATA_WIDTH 10
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0
#define LED_PIO_EDGE_TYPE NONE
#define LED_PIO_FREQ 50000000
#define LED_PIO_HAS_IN 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_TRI 0
#define LED_PIO_IRQ_TYPE NONE
#define LED_PIO_RESET_VALUE 0

/*
 * Macros for device 'dipsw_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'DIPSW_PIO_'.
 * The prefix is the slave descriptor.
 */
#define DIPSW_PIO_COMPONENT_TYPE altera_avalon_pio
#define DIPSW_PIO_COMPONENT_NAME dipsw_pio
#define DIPSW_PIO_BASE 0x10080
#define DIPSW_PIO_SPAN 64
#define DIPSW_PIO_END 0x100bf
#define DIPSW_PIO_IRQ 2
#define DIPSW_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define DIPSW_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define DIPSW_PIO_CAPTURE 1
#define DIPSW_PIO_DATA_WIDTH 10
#define DIPSW_PIO_DO_TEST_BENCH_WIRING 0
#define DIPSW_PIO_DRIVEN_SIM_VALUE 0
#define DIPSW_PIO_EDGE_TYPE ANY
#define DIPSW_PIO_FREQ 50000000
#define DIPSW_PIO_HAS_IN 1
#define DIPSW_PIO_HAS_OUT 0
#define DIPSW_PIO_HAS_TRI 0
#define DIPSW_PIO_IRQ_TYPE EDGE
#define DIPSW_PIO_RESET_VALUE 0

/*
 * Macros for device 'button_pio', class 'altera_avalon_pio'
 * The macros are prefixed with 'BUTTON_PIO_'.
 * The prefix is the slave descriptor.
 */
#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio
#define BUTTON_PIO_COMPONENT_NAME button_pio
#define BUTTON_PIO_BASE 0x100c0
#define BUTTON_PIO_SPAN 64
#define BUTTON_PIO_END 0x100ff
#define BUTTON_PIO_IRQ 1
#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 1
#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_DATA_WIDTH 2
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0
#define BUTTON_PIO_EDGE_TYPE FALLING
#define BUTTON_PIO_FREQ 50000000
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_IRQ_TYPE EDGE
#define BUTTON_PIO_RESET_VALUE 0

/*
 * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
 * The macros are prefixed with 'JTAG_UART_'.
 * The prefix is the slave descriptor.
 */
#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
#define JTAG_UART_COMPONENT_NAME jtag_uart
#define JTAG_UART_BASE 0x20000
#define JTAG_UART_SPAN 32
#define JTAG_UART_END 0x2001f
#define JTAG_UART_IRQ 0
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8


#endif /* _ALTERA_HPS_0_H_ */