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timing_simulation [2014/03/24 16:22]
timing_simulation [2014/11/02 12:20] (current)
janders [Example: dfmul benchmark]
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|run 6500000ps||run 6500000ps|
|+||IMPORTANT NOTE: Normally, for non-timing (RTL) simulation, we terminate the simulation and print the results when the finish signal goes HIGH. However, in timing sim, the results may not yet have settled when the finish signal goes HIGH. Recommend that you therefore wait 1/2 a cycle before the $display that prints the results.|