To run a timing simulation for Cyclone II on the DE2 board for the examples/chstone/dfmul benchmark:

1. Open the Quartus GUI. From project settings, set the EDA tools in Quartus to 'Modelsim' to generate a .vo file after synthesis.

2. Make a soft link to the .sdo file:

  cd examples/chstone/dfmul
  ln -s simulation/modelsim/top_v.sdo

3. Create a testbench dfmul_tb.v:

    `timescale 1 ns / 1 ns
    module main_tb ();
        reg  clk;
        reg  reset;
        reg  start;
        wire  finish;
        wire  [7:0] LEDG;
        wire [1:0] KEY;
        wire [15:0] SW;
        wire  [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;

        assign KEY[0] = reset;
        assign KEY[1] = start;

        de2 de2_inst (HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, LEDG,
            clk, KEY, SW);

        initial
            clk = 0;
        always @(clk)
            clk <= #10 ~clk;

        initial begin
        start <= 1;
        @(negedge clk);
        reset <= 0;
        @(negedge clk);
        reset <= 1;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        start <= 0;

        end

        initial
            $monitor("At t=%t %b %b", $time, HEX0, HEX1);
    endmodule

4. Then run Modelsim. Change the Cyclone II line if simulating another FPGA family. These commands can be put into a .tcl file:

    vlog dfmul_tb.v
    vlog simulation/modelsim/top.vo
    vlog /opt/altera11.1/quartus/eda/sim_lib/cycloneii_atoms.v
    vsim -t ps +transport_int_delays +transport_path_delays work.main_tb
    run 6500000ps

IMPORTANT NOTE: Normally, for non-timing (RTL) simulation, we terminate the simulation and print the results when the finish signal goes HIGH. However, in timing sim, the results may not yet have settled when the finish signal goes HIGH. Recommend that you therefore wait 1/2 a cycle before the $display that prints the results.