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timing_analysis_of_dfsin

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timing_analysis_of_dfsin [2013/06/26 12:55] (current)
yvonne.z1229 created
Line 1: Line 1:
 +Timing analysis of dfsin
 +
 +FMax: 59.89MHz
 +
 +Critical path: 19.494ns
 +
 +**Start signal: main:​main_inst|main_212_neg_i_i_i_i_reg[0]**
 +
 +**End signal: main:​main_inst|cur_state[0]**
 +
 +
 +/* main: %212*/
 +/*   %223 = add i64 %222, %.neg.i.i.i.i*/​
 +
 +**main_212_223 = (main_212_222_reg + main_212_neg_i_i_i_i_reg);​**
 +
 +/* main: %212*/
 +/*   %224 = icmp slt i64 %223, 0*/
 +
 +**main_212_224 = ($signed(main_212_223) < $signed(64'​d0));​**
 +
 +if ( ( ( (cur_state == LEGUP_F_main_BB_212_154) & (memory_controller_waitrequest == 1'd0)) & **(main_212_224 == 1'​d1)** ) )
 +**
 +cur_state <= LEGUP_F_main_BB__lr_ph_i_i_i_155;​**
 +
 +if ( ( ( (cur_state == LEGUP_F_main_BB_212_154) & (memory_controller_waitrequest == 1'd0)) & **(main_212_224 == 1'​d0)** ) )
 +
 +**cur_state <= LEGUP_F_main_BB_234_160;​**
 +
  
timing_analysis_of_dfsin.txt ยท Last modified: 2013/06/26 12:55 by yvonne.z1229