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'Vanilla' Profiling

  • A. Gordon-Ross, F. Vahid, “Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware,” IEEE Transactions on Computers, v.54 n.10, p.1203-1215, October 2005. pdf
  • R. Lysecky, S. Cotterell, F. Vahid, “A fast on-chip profiler memory,” Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA. pdf
  • L. Shannon, P. Chow, “Using reconfigurability to achieve real-time profiling for hardware/software codesign,” 2004 ACM/SIGDA, February 22-24, 2004, Monterey, California, USA. pdf
  • C. Zilles, G. Sohi, “A Programmable Co-processor for Profiling,” hpca, pp.0241, Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001. pdf

Power Profiling

  • X. Zhang, Z. Wang, N. Gloy, J. Chen, “System support for automatic profiling and optimization,” Proceedings of the 16th ACM symposium on Operating systems principles, p.15-26, October 05-08, 1997, Saint Malo, France. pdf
  • A. Sinha, A. Chandrakasan, “JouleTrack: a web based tool for software energy profiling,” Proceedings of the 38th conference on Design automation, p.220-225, June 2001, Las Vegas, Nevada, USA. pdf
  • H. Mehta, R. Owens, M. Irwin, “Instruction level power profiling,” IEEE International Conference, p.3326-3329, May 07-10, 1996. pdf
  • Y. Fei, S. Ravi, A. Raghunathan, N. Jha, “Energy Estimation for Extensible Processors,” Proceedings of the conference on Design, Automation and Test in Europe, p.10682, March 03-07, 2003. pdf
  • X. Feng, R. Ge, K. Cameron, “Power and Energy Profiling of Scientific Applications on Distributed Systems,” IPDPS'05, p.34, April 04-08, 2005. pdf
  • S. Song, R. Ge, X. Feng, K. Cameron, “Energy Profiling and Analysis of the HPC Challenge Benchmarks,” International Journal of High Performance Computing Applications, v.23 n.3, p.265-276, August 2009. pdf
  • J. Flinn, M. Satyanarayanan, “PowerScope: A Tool for Profiling the Energy Usage of Mobile Applications,” Second IEEE Workshop on Mobile Computer Systems and Applications, 1999. pdf
  • G. Qu, N. Kawabe, K. Usami, M. Potkonjak, “Function-level power estimation methodology for microprocessors,”“ Proceedings of the 37th conference on Design automation, p.810-813, June 05-09, 2000, Los Angeles, California, USA. pdf
  • A. Iyer, D. Marculescu, “Microarchitecture-level power management,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.230-239, June 2002. pdf
  • K. Lahiri, A. Raghunathan, S. Dey, “Efficient power profiling for battery-driven embedded system design,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.23, no.6, pp. 919-932, June 2004. pdf
  • Y. Hotta, M. Sato, H. Kimura, S. Matsuoka, “Profile-based optimization of power performance by using dynamic voltage scaling on a PC cluster,” Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006. pdf
  • G. Frantz, S. Subuvenkat, J. Bradley, “Processor Power Profiler,” US Patent #5,557,557, September 16, 1996. pdf - patent
  • C. Isci, M. Martonosi, “Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data,” 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'03), 2003 pdf

Cache Profiling

  • C. Zhang, F. Vahid, W. Najjar, “A highly configurable cache for low energy embedded systems,” ACM Transactions on Embedded Computing Systems (TECS), May 2005. pdf
  • C. Zhang, F. Vahid, R. Lysecky, “A self-tuning cache architecture for embedded systems,” ACM Transactions on Embedded Computing Systems (TECS), May 2004. pdf
  • C. Zhang, F. Vahid, W. Najjar, “A highly configurable cache architecture for embedded systems,” Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003. pdf

Value Profiling

profilers.txt · Last modified: 2010/12/15 15:53 (external edit)