Basic notes on how to do power analysis with Altera Quartus II PowerPlay using post-routing delays.
The following things need to be in the .qsf file
set_global_assignment -name EDA_SIMULATION_TOOL “ModelSim (Verilog)”
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT “VERILOG HDL” -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME /main_tb/top_inst -section_id eda_simulation
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
Here's how to generate the simulation netlist – telling Quartus what kind of VCD file (activity file) you want:
quartus_eda –format=verilog –glitch_filtering=on –read_settings_files=on –write_settings_files=on –simulation=on –tool=modelsim –vcd_type=all –vcd_tb_design_instance_name=/main_tb/top_inst top
Here's how to run vsim. Note that the “+acc” setting causes vsim to keep the SAME names as in the Verilog. This is needed otherwise Altera's PowerPlay cannot match up the names from the simulation and the netlist.
vsim -L work -L altera_ver -L stratixiv_ver +transport_int_delays +transport_path_delays work.main_tb -voptargs=“+acc” -c
Note that once vsim starts, you'll need to do something like this:
source top_dump_all_vcd_nodes.tcl
The above .tcl file is produced by quartus_eda and it tells vsim what signals you want to track in the simulation (for switching activity data).
Here's how to run PowerPlay.
quartus_pow top –input_vcd=simulation/modelsim/top.vcd –read_settings_files=on –vcd_filter_glitches=on
