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Pattern Sharing Introduction

In the Legup 1.0 release, which targeted Cyclone II, Binding shared only dividers and remainders.

Binding has been modified to share other types of operations, as well as larger computational patterns. This was shown to reduce area on Stratix IV, see here for more information.

Enabling and Disabling Pattern Sharing

The top of Binding.cpp contains the following macros:

// If set, div/rem will be shared with any required mux width
// (as in Legup1.0)
#define SHARE_DIV 1
#define SHARE_REM 1

// Maximum chain size to consider. Setting to 0 uses Legup1.0 
// original binding
#define MAX_SIZE 10

// If set, these will be included in patterns and shared with 
// 2-to-1 muxing
#define SHARE_ADD 1
#define SHARE_SUB 1
#define SHARE_BITOPS 1
#define SHARE_SHIFT 1

SHARE_DIV and SHARE_REM should always be set != 0, and will share these operations as in LegUp Release 1.0.

With SHARE_DIV and SHARE_REM set nonzero, setting MAX_SIZE to 0 will use the Binding in LegUp Release 1.0.

Setting SHARE_ADD, SHARE_SUB, SHARE_BITOPS and SHARE_SHIFT will share these operations when constructing computational patterns. Note that all 4 should be set when sharing for best results, but the macros provide a means for debugging. Setting these 4 all to 0 also results in the original LegUp Binding (equivalent to setting MAX_SIZE to 0). However MAX_SIZE takes precedence, so for example even if SHARE_ADD is set to 1, if MAX_SIZE = 0 then LegUp original Binding will be active.

I.e. both these examples will bind as in LegUp 1.0:

#define SHARE_DIV 1
#define SHARE_REM 1

#define MAX_SIZE 0

#define SHARE_ADD 1
#define SHARE_SUB 1
#define SHARE_BITOPS 1
#define SHARE_SHIFT 1
#define SHARE_DIV 1
#define SHARE_REM 1

#define MAX_SIZE 1

#define SHARE_ADD 0
#define SHARE_SUB 0
#define SHARE_BITOPS 0
#define SHARE_SHIFT 0

Writing Patterns to DOT and Verilog Files

Patterns found can also be written to .dot and .v files.

Setting the WRITE_TO_DOT macro to be nonzero will save all patterns of size > 1 to .dot files, and then convert these to .pdf files so that patterns may be visualized. The file name includes the pattern size and the frequency of occurrence.

The Graphviz graph visualization software can be downloaded from:

Similarly, for experimental purposes, it is possible to create a verilog module for each pattern, by setting the WRITE_TO_VERILOG macro nonzero. This creates a .v file for that specific pattern with the same filename as the .dot and .pdf files.

To avoid writing patterns of any frequency to these files, the macro FREQ_THRESHOLD lets only patterns shared with frequency greater than or equal to this threshold to be written to dot, pdf or verilog files.

The dot, pdf and verilog, files will be created in folders created for each function (given the function name).

binding_documentation.txt · Last modified: 2011/09/15 23:10 by stefan