LegUp High-Level Synthesis

Awards

We were delighted to receive the Community Award at FPL 2014 for contributions to open-source high-level synthesis:


This award is for authors who have made a significant contribution to the community by providing some material or knowledge in an open format that benefits the rest of the community. We sincerely thank the FPL community for the recognition.

Publications

  1. R. Nane, V.-M. Sima, F. Ferrandi, C. Pilato, J. Choi , B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, J.H. Anderson, K. Bertels, "A Survey and Evaluation of FPGA High-Level Synthesis Tools," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), October 2016. (PDF)
  2. A. Canis, J. Choi, B. Fort, B. Syrowik, R.L. Lian, Y.T. Chen, H. Hsiao, J. Goeders, S. Brown, J.H. Anderson, "LegUp High-Level Synthesis," chapter in FPGAs for Software Engineers, Springer, 2016. (Link)
  3. J. Choi, R. Lian, S. Brown, J.H. Anderson, "A Unified Software Approach to Specify Pipeline and Spatial Parallelism in FPGA Hardware," IEEE Int'l Conference on Application-specific Systems, Architectures and Processors, London, UK, July 2016. (PDF)
  4. S. Hadjis, A. Canis, R. Sobue, Y. Hara-Azumi, H. Tomiyama, J. Anderson, "Profiling-driven multi-cycling in FPGA high-level synthesis," ACM/IEEE Design Automation and Test in Europe Conference (DATE), Grenoble, France, in March 2015. (PDF)
  5. N. Calagar, S. Brown, J.H. Anderson, "Source-Level debugging for FPGA high-Level synthesis," IEEE International Conference on Field-Programmable Logic and Applications (FPL), Munich, Germany, September 2014. (PDF)
  6. A. Canis, J.H. Anderson, S.D. Brown, "Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis," IEEE International Conference on Field-Programmable Logic and Applications (FPL), Munich, Germany, September 2014. (PDF)
  7. B. Fort, A. Canis, J. Choi, N. Calagar, R. Lian, S. Hadjis, Y.T. Chen, M. Hall, B. Syrowik, T. Czajkowski, S.D. Brown, J.H. Anderson "Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis," Int'l Conference on Embedded and Ubiquitous Computing (EUC), Milan, Italy, August 2014. (Invited paper). (PDF)
  8. Q. Huang, R. Lian, A. Canis, J. Choi, N. Calagar, R. Xi, S. Brown, J.H. Anderson, "The effect of compiler optimizations on high-level synthesis-generated hardware," to appear in ACM Transactions on ReconīŦgurable Technology and Systems (TRETS), 2014.
  9. Jongsok Choi, Stephen D. Brown, and Jason H. Anderson, "From Software Threads to Parallel Hardware in High-Level Synthesis for FPGAs," Int'l Conference on Field-Programmable Technology (FPT), Kyoto, Japan 2013. (PDF)
  10. Ana Klimovic and Jason H. Anderson, "Bitwidth-Optimized Hardware Accelerators with Software Fallback," Int'l Conference on Field-Programmable Technology (FPT), Kyoto, Japan 2013. (PDF)
  11. Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen D. Brown, Jason H. Anderson, "From C to Blokus Duo with LegUp High-Level Synthesis," Int'l Conference on Field-Programmable Technology (FPT), Kyoto, Japan 2013. (PDF)
  12. A. Canis, J. Choi, B. Fort, R. Lian, Q. Huang, N. Calagar, M. Gort, J.J. Qin, M. Aldham, T. Czajkowski, S.D. Brown, J.H. Anderson, "From Software to Accelerators with LegUp High-Level Synthesis," Int'l Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Montreal, September 2013. (PDF)
  13. Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, J. Anderson, "The effect of compiler optimizations on high-level synthesis for FPGAs," IEEE Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, WA, May 2013. (PDF)
  14. Andrew Canis, Stephen D. Brown, and Jason H. Anderson, "Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis," Design, Automation, and Test in Europe (DATE). Grenoble, France, March, 2013. (PDF)
  15. Marcel Gort and Jason H. Anderson, "Range and Bitmask Analysis for Hardware Optimization in High-Level Synthesis," Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January, 2013. (PDF)
  16. A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, T. Czajkowski, S. D. Brown, and J. H. Anderson, "LegUp: An Open Source High-Level Synthesis Tool for FPGA-Based Processor/Accelerator Systems," ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 2, p. 24, 2013. (PDF)
  17. Jongsok Choi, Kevin Nam, Andrew Canis, Jason H. Anderson, Stephen Brown, and Tomasz Czajkowski, "Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems," IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, Canada, April 2012. (PDF)
  18. S. Hadjis, A. Canis, J.H. Anderson , J. Choi , K. Nam, S. Brown, T. Czajkowski, "Impact of FPGA Architecture on Resource Sharing in High-Level Synthesis," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2012. (PDF)
  19. M. Aldham, J.H. Anderson, S. Brown, A. Canis, "Low-Cost Hardware Profiling of Run-Time and Energy in FPGA Embedded Processors," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Santa Monica, CA, September 2011. (PDF)
  20. A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J.H. Anderson, S. Brown, T. Czajkowski, "LegUp: High-level synthesis for FPGA-based processor/accelerator systems," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 33-36, Monterey, CA, February 2011. (PDF)