LegUp High-Level Synthesis

LegUp 3.0 Online Demo

Unfortunately the online demo doesn't use LegUp 4.0

The LegUp 3.0 demo will synthesize your C code into Verilog RTL running entirely in hardware (no soft TigerMIPS co-processor). The demo uses the default LegUp settings: Cyclone II FPGA target device, 15ns period constraint, binding enabled for dividers, and pattern sharing enabled. The default code is the MIPS benchmark from CHStone, which implements a MIPS processor and then executes a short MIPS program to sort an 8 integer array.

Enter the C code you wish to synthesize into Verilog:

Warning: We store all submissions to help us improve LegUp. But they will never be released to third parties.